(1) Field of the Invention
The present invention relates generally to a method of forming a semiconductor device, and more particularly to form a radio frequency (RF) inductor on a semiconductor substrate, using continuous metal deposition.
(2) Description of the Prior Art
Monolithic inductors built on silicon substrates are widely used in CMOS based RF circuits such as, low-noise amplifiers, voltage-controlled oscillators, and power amplifiers. One of the most important characteristics of the inductor is the quality factor Q, since it affects the performance of the RF circuits and systems. The spiral inductors implemented in the standard CMOS process, however, suffer from poor Q due to the lossy property of the CMOS substrate and thin metal layers from which the inductors are formed. In addition, the planar inductor takes up a large die area resulting in long inter-connect lines among the active and passive devices in a chip. Long interconnect lines in turn cause excess signal losses due to parasitic resistance and capacitance. The larger die area also increases the cost of the RF integrated circuit (IC).
In CMOS technology, on-chip inductors suffer from three main loss mechanisms: ohmic, capacitive, and inductive. Ohmic losses are due to current flowing through the resistance of the metal tracks. Using wider metal lines can reduce ohmic losses but will also increase the capacitive losses and will also decrease Q from the resulting larger metal-to-substrate capacitance. The displacement currents conducted by the metal-to-substrate capacitance result in capacitive losses; and the eddy currents generated by the magnetic flux penetrating into the substrate result in inductive losses.
U.S. Pat. No. 6,187,647 B1 describes a method of manufacturing lateral high-Q inductor for semiconductor devices. The method comprises of the steps of forming the bottom legs on a first substrate; depositing a second substrate layer over the first substrate; forming the pair of side legs for each loop through the second substrate layer; and forming top legs connecting pairs of side legs extending from adjacent bottom legs. The step of forming the side legs included forming a pair of vias through the second substrate layer to the bottom legs and depositing side legs in the vias. The step of forming the top legs includes forming a channel between the pairs of vias respectively communicating with the adjacent bottom legs and depositing top legs in the channels.
U.S. Pat. No. 6,201,287 B1 describes monolithic inductance-enhancing ICs, CMOS inductance-enhancing ICs, inductor assemblies, and inductance-multiplying methods. In one embodiment, a monolithic inductance—enhancing IC comprises a transistor supported by a bulk mono-crystalline silicon substrate. An inductor assembly is supported by the substrate and connected with the transistor in an inductance-enhancing circuit configuration having a Q factor greater than 10. In another embodiment, a CMOS inductance-enhancing IC includes a FET device, supported over a silicon-containing substrate and is connected to the gate. A second inductor is received within the insulation layer and connected to the source. The first and second inductors are arranged in a feedback loop, incorporating the FET device. In another embodiment, a monolithic substrate is provided on which CMOS IC is formed and includes an FET device and a pair of inductors. The configuration of the FET and the pair of inductors is such as effectively increase the inductance of one of the inductors.
U.S. Pat. No. 6,309,922 B1 describes a method of fabricating on-chip inductors and related structure. According to one embodiment, inductors are formed by patterning conductors within a dielectric in a semiconductor die. The entire dielectric layer is then subjected to blanket implantation or sputtering of high permeability material. In another embodiment, a first area of in a semiconductor die is covered with a photo-resist, while the second area includes a patterned conductor used as an inductor. The patterned conductor is also covered with photo-resist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability material in the dielectric results in the inductors having higher inductance than they would have otherwise.
U.S. Pat. No. 6,329,234 B1 describes both a structure and a method of fabricating both copper metal-insulator-metal (MIM) capacitor and thick metal inductors, simultaneously using one mask. The process uses damascene and dual damascene trench/via process. High performance device structures formed by this invention include, parallel plate capacitor bottom metal electrodes and capacitor top metal electrodes, MIM capacitors, thick inductor metal wiring, interconnects and contact vias.